Effective SoC test requires a range of verification solution upgrades, such as:
Specification-driven, abstract test content composition
Increased “temporal” coverage and debug for finding and tracking complex, concurrent corner-cases
Platform portability for “shift-left” efficiencies
Configurable, re-usable system test content
The advent of the Synthesizable VerificationOS, a lightweight kernel that drives verification specific services, test scheduling and execution management across ARM and RISC-V SoCs, holds the answer to many of these challenges. Driven by PSS 2.0, C++, UVM and other formats, the SV-OS accelerates, simplifies and increases the coverage across the most complex of SoC verification programs.
3 Key Points:
Synthesizable VerificationOS accelerates and simplifies software-driven SoC verification
SoC verification quality requires temporal coverage to track down complex corner case bugs
SoC verification may be accelerated through shift-left techniques requiring portable test content and reusable, configurable system test IP
Dave Kelf, is responsible for Breker’s marketing activities, strategic programs and channel management. Dave most recently served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier, Kelf was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, noted for the Verdi product line, which became Springsoft and is now part of Synopsys.
Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.
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