Nick Jones, Senior Staff Engineer, Samsung Austin R&D Center
This presentation describes a methodology for reuse of stimulus from an integrated chip testbench at the unit level with UVM and an embedded key/value store. The methodology leverages monitoring UVM sequence items in an integrated, passive UVM Verification Component (UVC) and storage into LevelDB. Replay of these stored items provides cycle accurate stimulus at the unit level for accelerated debugging and regression.
Nick’s background stems from a lifelong love of learning programming languages, to post-silicon lab debug, and design verification. He has most recently been working on verifying an ARM compliant custom CPU for SARC’s next generation IP.
When he’s not working, he’s playing with his kids, triathlon training, or home brewing beer