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ML Verification Turns Convention on its Head

DVCLUB Europe | Verification of AI Designs

ML Verification Turns Convention on its Head

Conference:DVCLUB Europe | Verification of AI Designs
Speaker:Adnan Hamid, CEO/CTO, Breker Verification Systems
Abstract:The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

  • Current verification methodologies cannot scale to meet ML processor challenges
  • ML verification approach: consider desired outputs, optimize inputs to match
  • Test Suite Synthesis enable planning algorithm approach to target ML requirements
Speaker Biography:Adnan is the founder and CEO of Breker and the inventor of its core technology. Under his leadership, Breker has come to be a market leader in next-generation functional verification technologies. He has over 20 years of experience in functional verification automation. Prior to Breker, he managed AMD’s System Logic Division, and also led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor. In addition, Adnan spent several years at Cadence Design Systems and served as the subject matter expert in system-level verification, developing solutions for Texas Instruments, Siemens/Infineon, Motorola/Freescale, and General Motors. Adnan holds twelve patents in test case generation and synthesis. He received BS degrees in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.

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