Sharon Rosenberg, Senior Solution Architect, Cadence Design Systems
The Accellera PSS1.0 that was released at DAC 2018 is conceptually different than HW verification languages. Obviously, PSS already specifies how to create scenarios, and how to make these portable across platforms, thus sequences are not needed. Still there is a lot of commonality between SOCs that can be leveraged for a common methodologyand even codified in a standard library. This paper answers many questions that user may ask himself before writing his first PSS file:
How can I ensure future integration of my code with other PSS models?
Is there a UVM version of PSS? What features will be in it and how would it look like?
What are the coding styles for my home-grown development or commercial PSS VIP selection?
Sharon Rosenberg is a senior architect at Cadence. Sharon received his B.A. in computer science from Bar-Ilan University and joined Verisity Design in 1996 to lead the hardware testbench automation revolution. He introduced many of the most used UVM concepts, including agents, factory, configuration mechanism, and sequences as the technical leader of the Cadence UVM team.
Sharon represented Cadence in the Accellera UVM working group and co-authored the book A Practical Guide to Adopting the Universal Verification Methodology. Currently Sharon is driving portable stimuli solution technology for SoC verification and represents Cadence in the Accellera Portable Stimulus Working Group.
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