Portable Stimulus from IP to SoC – Achieve More Verification2018-08-08T09:48:51+00:00

DVCLUB Europe |Portable Stimulus

Portable Stimulus from IP to SoC – Achieve More Verification

Conference:DVCLUB Europe | Portable Stimulus | Sep 2018
Speaker:Tom Fitzpatrick, Verification Technologist – Mentor, A Siemens Business
Abstract:With so much of the buzz about the emerging Accellera Portable Stimulus Standard centered around applications in the system level space, it might seem that this is the sole application for the technology. However, users have long been applying portable stimulus techniques across block, subsystem, and SoC-level environments to improve their verification productivity. This presentation will show how Mentor’s in Fact portable stimulus tool is applied across the verification spectrum and the spectrum of verification engines to achieve more verification with the same resources.
Speaker Biography:Tom Fitzpatrick is a Strategic Verification Architect at Mentor, A Siemens Business where he works on developing advanced verification methodologies and educating users on their adoption. He is currently responsible for Mentor’s Safety-Critical Verification strategies. He has been a significant contributor to several industry standards, both in Accellera and IEEE, including Verilog 1364, SystemVerilog 1800, UVM and currently serves as the Vice Chair of the Portable Stimulus Working Group.

He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification, Portable Stimulus and other functional verification topics. Tom holds Master’s and Bachelor’s degrees in EE/CS from MIT.

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