A typical hardware design verification environment includes several features to be included and used for a successful sign-off. To start with, the environment must contain support for robust constraint random test sequence generation targeting different design specification features. Along with that, it should support various test bench component development like drivers, monitors and scoreboard to interact with the design RTL and reference model. To aid the model interactions, the environment must provide hooks to talk to third party reference models written in other platforms like C, C++ or Matlab. It is also important that the environment supports waveform generation for debug and functional coverage definitions for verification sign-off. Traditionally, SV/UVM framework has been used to cater to all the above verification needs.
In order for Python to succeed as a choice of language for verification, Python packages like cocotb  and cocotb-coverage  provide the support for developing the various verification environment features listed above. Using these packages guarantees that the productivity and ease of Python adoption is possible without compromising the quality of verification. CoCoTb is a Python plugin to RTL simulator and also includes a library for writing synchronous logic. In other words, CoCoTb provides standardised interfaces like VPI, VHPI to talk to the simulators. This enables any Python verification test bench to link to the RTL simulator thereby reaching into the DUT hierarchy to read or modify values. In addition to this, CoCoTb library provides ways to develop the Python test bench components like Input Drivers, Input/Output Monitors and Scoreboard to support a generic verification framework. The CoCoTb-Coverage package supports definitions for constraint random generation as well as functional coverage definition. This facilitates a unified framework in Python meeting all the verification requirements.
Shakti processor  verification predominantly uses CoCoTb based environments for verifying processor blocks like compute and load/store units. The whole environment is developed in Python and the RTL is simulated using Verilator . The Python packages seamlessly aid in quick environment bringup and speed up verification with highly parallelised simulation runs with this open source setup. At processor level, constraint random RISC-V assembly programs are used in a CoCoTb test bench where a third party C++ Instruction Set Simulator (ISS) is used for processor state checking at every instruction execution. In conclusion, verification in Python is the new normal facilitating an open source flow in processor verification.
Using CoCoTb and its support packages guarantees hardware design verification without compromising on verification quality
RISC-V Processor Verification in Python is a new reality
CoCoTb-Verilator setup facilitates open source verification flow
With a background in MS at IIT Madras, Chennai, India, Lavanya has predominantly worked in various processor verification teams with IBM, ARM and Rambus for around 7 years. For the past 3 years, she has been leading the verification efforts at IIT Madras with Shakti Team working on research and development efforts on RISC-V based processor systems.
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