DV engineers determine when the RTL is good to ship. We set our own criteria for this. So it’s no surprise we can be a bit neurotic. If we had no project timescale pressures we would always think of more and more testing we could do to give us a tiny bit more confidence in the design and we’d never actually ship the product. However, DV completes after design and often after physical layout is complete too, so our signoff is often the gating factor for tapeout itself.
So when balancing doing all the verification we can think of against the commercial pressures of delivering products quickly, how do we decide when we are done? Also, what can be done to speed up the sometimes slow signoff / delivery process?
3 Key Points:
Review possible signoff criteria.
Consider what signoff criteria are essential and must gate delivery and what criteria, when pushed, we can be more pragmatic about.
Consider how the bureaucratic signoff process can be left shifted to deliver more quickly.
Before joining Graphcore less than a year ago Anthony has worked as a CPU and GPU design and verification engineer at Infineon, Xmos and Imagination. At Imagination he was head of verification for the high end GPU cores where his duties included defining the verification process and the signoff procedure. As formal verification team lead at Graphcore he is tasked with leveraging formal techniques throughout the silicon team.
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