The BootROM of an SOC is traditionally considered software and, hence, is verified by software teams. Since BootROM is fabricated as part of the SOC, and is therefore immutable after tape-out, functional errors have the potential to trigger a respin. To ensure functional correctness as early in the design cycle as possible, using hardware verification methodologies for BootROM verification can be of great help.
These methods include constrained random stimulus generation, automated checking, and use of coverage tools to measure quality. The SystemVerilog constraint solver can be used for randomizing various boot configurations. A checker can observe events using monitors and ensure that the SOC is being configured correctly at each boot stage. Coverage can be obtained by parsing simulation logs and mapping it to disassembled boot code. During this presentation, we will talk through the implementation of these methods at a high level. We will share our experiences, as well as limitations and benefits of these techniques
Aman Arora is an engineer working at NVIDIA for the past 7 years. He has worked on a variety of verification roles including methodology, infrastructure, SOC level verification, unit level verification, and Silicon bringup. He graduated from the University of Texas at Austin in 2012. He likes doing yoga, going on hikes, and listening to podcasts.
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