DVCLUB Europe | Using Python in Verification

Using Python in Verification

Conference:DVCLUB Europe | Using Pythom in Verification
Speaker:Ray Salemi, Aerospace and Defence Solutions Manager, Siemens Digital Industries Software

A LinkedIn search for SystemVerilog shows 60,000 profiles that name the language.  A LinkedIn search for Python shows 6,000,000. 100x
As Aerospace and Defenense companies have found it challenging to hire SystemVerilog engineers, and VHDL lacks modern language features such as object-oriented programming,

Perhaps the solution is to write our benches in Python.

3 Key Points:

  • Python is a much easier language to use than SystemVerilog or VHDL because of its lack of typing
  • cocotb is a robust Python package that connects Python to a DUT
  • pyuvm is an implementation of the UVM in Python, bringing modern reuse to Python verification engineers
Speaker Biography:

Ray Salemi is the Aerospace and Defense Solutions Manager for the IC Verification Solutions Division of Siemens DISW. A former Mentor Graphics verification consultant working with aerospace and defense companies, Ray holds a Bachelor of Science in Computers Systems Engineering from the University of Massachusetts at Amherst and an MBA from Babson College. In his current role, he ensures that Siemens IC verification solutions meet the needs of Aerospace and Defense companies.

He is the author of FPGA Simulation and The UVM Primer.


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