In recent times, there is an increased adoption of RISC-V based implementations amongst Product R&D or R&D Service Organizations. These RISC-V cores are either developed within the organization or customized using the available open source RISC-V cores targeting their specific applications.
In order to verify these highly configurable RISC-V based SoCs, there is a need to make the verification environment also configurable to achieve rapid verification quality before tapeout. To aid this end goal, we propose an automated generation of the verification test bench modules and the SoC verification environment. This makes the environment more robust by avoiding human errors during test bench development thus improving productivity. The talk will cover the following topics adopted as a standard approach of verifying a readily available open source RISC-V based SoC and the steps to achieve value addition during the verification process
Bridge/Interconnect customized block features can be verified using automated generation of reusable, parameterized UVM VIPs
Automated build of test bench environment, top file creation, hierarchical signal connection files etc.
Reducing SoC integration time and avoiding manual errors by automating the required test bench files and re-using block level verification components
Suresh babu has overall industry experience of 19+ Years. He is a key member of Tessolve Technical and Delivery team and performs the role of a Solutions Architect for all Key Customer Engagements related to the APAC Region (Korea and Japan). He also plays a key role in defining the Tessolve VIP Architecture and overseeing the VIP program within Tessolve. Currently he is leading a large team and performing Verification of an Advanced Memory Subsystem for a handset application manufacturing OEM and he has architected the complete flow from Specification to Signoff. He also leads the EDA Productivity Tools BU where he has played an important role in defining the requirements of the productivity tool (asureRAL, asureRUN, asureCode) and guiding the team to complete it.
Lavanya is the Co-Founder and VP Verification Systems at InCore Semiconductors. At InCore, she pioneers open source verification frameworks for RISC-V based subsystems. She has 7+ years experience in industry as part of various processor verification teams and has been leading the verification efforts with the Shakti Program at IIT Madras for the past 2.5 years
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