Name:Prem C K
Designation:Sr.Member of Technical Staff, AMD
Title:SoC Design Verification using 3rd party IPs – Challenges & Guidelines


This presentation is about the verification challenges if a given SoC has design/verification components that are sourced from 3rd party vendor(s).

It covers the important considerations from verification planning to pre-silicon through tape-out.It also covers few guidelines that would help to address the issues that may potentially compromise the verification quality.

Key Points:

  • Interoperability of Vendor IPs.
  • Test planning considerations.
  • Coverage planning considerations.


  • 15+ years of Verification work experience on IP, Sub-System and System Level.
  • Hands on Experience in Pre and Post silicon Validation.

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