|Designation:||Sr.Member of Technical Staff, AMD|
|Title:||SoC Design Verification using 3rd party IPs – Challenges & Guidelines|
This presentation is about the verification challenges if a given SoC has design/verification components that are sourced from 3rd party vendor(s).
It covers the important considerations from verification planning to pre-silicon through tape-out.It also covers few guidelines that would help to address the issues that may potentially compromise the verification quality.
- Interoperability of Vendor IPs.
- Test planning considerations.
- Coverage planning considerations.
- 14+ years of work experience in multimillion gates ASIC/SOC functional verification. Familiar with standard ASIC design flow from design concept to tape-out. Have participated in many multi-million gate SOC tape-outs.
- Has worked hands-on with the development of module/chip-level test plans and verification infrastructure encompassing state of art Verification IPs.
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