Name: | Vedantham Krishnan |
Designation: | Sr.Member of Technical Staff, AMD |
Title: | SoC Design Verification using 3rd party IPs – Challenges & Guidelines |
Abstract:
This presentation is about the verification challenges if a given SoC has design/verification components that are sourced from 3rd party vendor(s).
It covers the important considerations from verification planning to pre-silicon through tape-out.It also covers few guidelines that would help to address the issues that may potentially compromise the verification quality.
Key Points:
- Interoperability of Vendor IPs.
- Test planning considerations.
- Coverage planning considerations.
Biography:
- 14+ years of work experience in multimillion gates ASIC/SOC functional verification. Familiar with standard ASIC design flow from design concept to tape-out. Have participated in many multi-million gate SOC tape-outs.
- Has worked hands-on with the development of module/chip-level test plans and verification infrastructure encompassing state of art Verification IPs.
View the Presentation Material: