|Designation:||Senior Engineer,Test and Verification Solution,Singapore PTE LTD|
|Title:||Co-Verification for Complex SoC Designs|
Introduction: As more and more electronic products have extensive software content, designers are faced with serious project delays if they wait for first silicon to begin software debugging. Indeed, “first software” becomes the pacing milestone for product delivery.
Increasingly, developers are turning to hardware/software co-verification — concurrently verifying hardware and software components of the system design — to deliver on more demanding time-to-market requirements. Concurrent verification allows software verification and debugging to begin before silicon is available, often before it is frozen, which can shave months off the software development schedule.
Objectives of HW/SW co-verification :
The traditional approach to software verification is to wait for (mostly) working silicon to begin software debugging. This makes the hardware and software debugging tasks largely sequential, and increases the product’s development time. It also means that a serious system problem may not be found until after first silicon, requiring a costly respin and delaying the project for 2-3 months.
The objective of co-verification is to make the hardware and software debugging tasks as concurrent as possible. At a minimum, this means starting software debug as soon as the IC is taped out, rather than waiting for good silicon. But even greater concurrency is possible. Software debugging with the actual design can begin as soon as the hardware design achieves some level of correct functionality. Starting software debugging early can save from 2 to 6 months of product development time.
Approaches to HW/SW co-verification :
Emulation can be used as a vehicle for hardware/software co-verification – supporting real world data for comprehensive system testing, and a complete software debugging environment.Emulation also provides a platform to evaluate hardware/software implementation tradeoffs early in the design cycle. Potential software performance bottlenecks can be uncovered while there is still time for a hardware-based solution.Co-verification can also be achieved by ISS models, RTL processor models and FPGA based boards.
Advantages of co-verification :
Co-verification is a productive approach to minimise the overall product development turn-around time. Some significant advantages for SoC Design are as listed below
- Co-verification is helpful for “Application Usecase verification”
- Co-verification environment can also be used for system stress testing
- Emulation supports co-verification and has good EDA support
Software content of electronic products is increasing exponentially and is most often the pacing item for product completion. Software simulation alone is not fast enough to test the volume of software being written for today’s electronic products. Using acceleration and emulation for hardware/software co-verification takes advantage of the made in the emulator for SoC verification to speed software debugging thus shortening product cycles by several months.
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