Are we Ready for New set of Verification challenges fling by Automotive SoC’s !!2018-09-03T07:10:04+00:00
Conference:DVClub India – September 2018  (click here to see full programme)
Speaker:Lokesh Babu Pundreeka, Technical Director , System Verification Group, Cadence Design Systems
Presentation Title:Are we Ready for New Set of Verification Challenges Fling by Automotive SoC’s !!
Abstract:Autonomous driving is becoming real and it is demanding more safe and secure Electronic components (IC’s) for making autonomous vehicle are Safety and reliable. Experience and learning from consumer and mobile ASIC’s design and verification may not enough to meet requirements for Automotive SoC’s.  In this talk, we will explore some challenges in designing and verification of Automotive SoC’s and how we can overcome these challenges with cadence solutions.
Speaker Biography:Lokesh Babu is holding 16+ years of experience in Mobile and Automotive ASIC’s Design and Verification. He started his carrier at Texas instruments (TI) as a Sr. Design Engineer and at TI worked on Design and Verification of High Speed Emulation Chip and 802.11 a/b/g WIFI chips. In last 11+ years at Cadence, he is driving System Verification Application Engineering team, primarily focused on new methodologies like Assertion based Formal Verification, UPF/CPF/1801 based Low Power Methodology, Automotive ISO26262 Functional Safety and Security and Portable Test and Stimulus Standard (PSS).

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