Name:Alex Netterville
Designation: Senior Engineer
Title:Formal – Leaving the nest

Abstract: Faced with challenges in gaining adoption, Formal verification now has high level buy-in at ARM. This presentation explores some of these adoption issues and solutions from the perspective of a new product development called “Pelican”. It explores past, present and new methodologies coming online and discusses concepts where formal is of high value, or has unique qualities to offer. It is very much a whistle stop tour, from high level architectural verification to buried interface contracts. It ends with a set of areas for EDA vendors to ponder from our formal wish list at ARM

Biography : Alex Netterville has been working at ARM for nearly ten years, and got the bug for formal while working on property synthesis and wiring scripts for FPGA as a summer placement. He went on to write his final year thesis on this topic. Upon joining ARM permanently, he was working on CPU cores in both design and verification capacities equally, and has done so ever since on a range of ARM cores out in the market. Having done formal AND simulation test benches, formal won the day for him and he is now an ardent advocate for this technology in all aspects of design and verification. Where there’s an interesting question to be asked about a design, chances are he’s tried asking it, and when he isn’t doing that he’s leading a team of engineers on new developments looking at rolling formal verification out to the masses

Formal Verification Seminar Presentation                                                                    Video Presentation