|Title:||Using Formal in the Design of Interfaces and Verification IP|
This paper proposes the development of verification IP should be a fundamental part of interface design. It shows that applying formal to the design of VIP can help make test benches more reliable and ensure that interface assertions are more complete.
Geoff completed his DPhil thesis on the formal verification of the Transputer in 1988. He has published 20+ papers on formal verification and written a formal equivalence checker and a CTL model checker while at ST in the ‘90s. More recently, Geoff has developed simulation-based verification methodologies and leads the verification methodology activity in Broadcom’s Broadband Communications Group.
Formal Verification Seminar Presentation Video Presentation