Name:Tim Blackmore
Designation:Verification Manager
Title:Using Formal Methods in Safety Verification

Abstract: Over time hardware can degrade and it is important that any degradation that can affect safety critical applications can be detected. Hardware and software safety mechanisms are used to detect such faults and safety standards, such as ISO262626, require you to quantify how sensitive to faults these mechanisms are. A fault coverage in excess of 99% may be required and this is usually measured with fault simulations. For such high coverage requirements it is necessary both to identify which logic is safety critical (and so is covered by safety mechanisms) and to have high quality stimuli. This presentation describes some early work on using formal methods to help achieve both of these requirements.

Biography: Tim manages a team responsible for CPU, IP and subsystem verification. He has worked across all the usual verification methodologies and, in particular, has been working in formal verification for over 13 years. Prior to working in verification he obtained a Ph.D. in Pure Mathematics and worked as a research fellow, publishing in leading maths and engineering journals.

Formal Verification Seminar Presentation                                                                                Video Presentation