Conference:Formal Verification 2017
Speaker:Vincent Reynolds, (Senior Product Engineer Formal R&D) Cadence
Presentation Title:A Modern Approach to Multi-Engine Metric Driven Verification
Abstract:For many years, formal technology has steadily evolved from humble beginnings to gaining acceptance and recognition for the value it brings to the verification challenge. In the early days, specialist PhD graduates were needed to write properties and even then, only relatively simple designs could be analysed. Today the capacity has grown to accommodate much larger designs and can even operate on some system-level environments. With the simplicity of apps for specific tasks and the flexibility of assertion languages that enable even novice users to develop customised environments, there has never been a better time or so many opportunities to deploy formal. Despite all this, formal is often still seen as an optional side activity to mainstream simulation and does not directly contribute to the final sign-off goals. This talk will introduce new tool capabilities and associated methodologies that promote the efficient and complimentary deployment of both formal and simulation throughout the project life-cycle ultimately enabling earlier tape-outs with higher quality designs.

  • Shift left verification
  • Sign-off with formal
  • Multi-engine MDV
Speaker Bio:Vincent Reynolds is a leading formal verification expert and a member of the JasperGold product expert team at Cadence. He has extensive experience working with customers to deploy practical engineering solutions on live projects using the latest tools and technologies. Vincent joined Cadence in 2004 following several years at the UK-based start-up BlueArc (now Hitachi) working in a small team on the development of an FPGA based enterprise storage solution. Prior to BlueArc Vincent started his career at Nortel Networks working as a designer of high-end packet switching ASICs. During his time at Nortel Vincent worked at multiple sites throughout the UK and North America and gained experience of a wide range of design and verification techniques. Vincent holds a BEng degree in Microelectronic Systems Engineering from Brunel University.

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