University of Bristol
|Designation:||Head of the Microelectronics Research Group , University of Bristol|
|Title:||Building HPC Systems from Mobile Processors: The Mont Blanc Project|
Abstract: Energy efficiency is becoming the limiting factor in large scale high performance computing systems. Today’s fastest machines already use megawatts of power and cost millions of dollars a year to run. By the end of this decade the fastest machines are predicted to require over 20 megawatts of power, making them considerably more expensive to run than today’s machines, and limiting the number of sites that can support such machines. To address this issue, the Mont Blanc project is investigating whether technologies being driven by the mobile markets may help address the energy efficiency crisis in HPC. This talk will describe the prototype machines which have been built using mobile processors, and present the results so far.
Biography : McIntosh-Smith has spent most of his life designing and programming multi-core and many-core systems. He began his career as a microprocessor architect at Inmos and STMicroelectronics, before co-designing the world’s first fully programmable GPU at Pixelfusion in 2000. In 2002 he co-founded ClearSpeed where, as Director of Architecture and Applications, he co-developed the first modern many-core HPC accelerators. In 2003 he led the development of the first accelerated BLAS/LAPACK and FFT libraries. This is turn gave rise to the first modern accelerated Top500 system, TSUBAME 1.0 at Tokyo Tech in 2006. He now leads the Microelectronics Research Group at the University of Bristol, UK. He is a member of the project group leading the design of Archer, the next UK national supercomputer, where he takes particular responsibility for advanced technologies, such as heterogeneous computing. He sits on the Khronos industry standards body and actively contributes to the OpenCL heterogeneous many-core programming standard. He is a member of the EU-funded European Exascale Software Initiative (EESI), sits on PRACE funding panels, chairs the Many-core and Reconfigurable Supercomputing Conference (MRSC), and sits on the program committees for SC, ISC and HiPEAC.