Name:Francois Cerisier
Designation:Manager, TVS France
Title:Interconnect Verification

Abstract:  The increase of SoC complexity with more cores, IPs and other subsystems has led SoC architects to demand more from the main interconnect or NoC, which becomes a key component of the system.  Power management, multiple clock domains, protocol conversions, security management, virtual address space, cache coherency are now key features that the main interconnect needs to manage and which demand proper verification.

In addition, IP reuse and Network-on-Chip (NoC) generation solutions have enabled the conception of new SoC architectures within a few months if not only weeks.  While a simple point to point scoreboard methodology is taught in all good verification methodology books or tutorials, building a generic verification solution for SoC interconnect that can quickly adapt to any bus protocols, SoC architectures and deal with SoC advanced features is much more than dealing with point to point transaction matching.

At Test and Verification Solutions (TVS) we have developed a UVM NoC Scoreboard VIP to provide a generic approach for interconnect, fabrics and NoC verification and accelerate this verification.

Biography:  François Cerisier has an Engineering Diploma in Digital Signal Processing from Polytech’Sophia, University of Nice-Sophia-Antipolis and over 13 years of experience in verification of IPs, CPUs and System-On-Chips and in hardware/software co-verification. François gained verification methodology expertise from industrial projects of major semiconductor companies (including Infineon, Broadcom, ST-Microelectronics, ST-Ericsson) and EDA start-ups. He is now leading Test and Verification Solutions subsidiary in France to provide verification services and consulting.

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