Name:Sergio Marchese
Designation:Senior Field Application Engineer
Title:IP Design and Integration Verification Utilising Formal Technologies

Abstract : Leveraging real world experience from leading semiconductor companies, this presentation will discuss a methodology to provide a thorough and rigorous test of the integration of third party Intellectual Property (IP) into systems. Using Assertion Based Verification (ABV) techniques and static verification solutions, a proven solution to IP integration will be discussed that has a direct impact on integration quality while also improving the speed and efficiency of system verification in general.

Biography : Sergio Marchese has 13 years of experience in the semiconductor industry in the areas of hardware verification and Design for Test (DFT).  Marchese has worked with numerous EDA and ASIC/FPGA development companies, from large and established organizations to startups in Europe, the United States and Japan.  He has held multiple positions with responsibilities in technical marketing, pre-sales support, project planning and execution.  Marchese’s area of expertise is formal verification and his achievements include: building and leading a team of formal experts to verify a large portion of a communication SoC; developing a property-based transaction-level model of a configurable IP; and integrating automated formal verification solutions into corporate design flows.  Marchese earned a Master of Science degree in Electronic Engineering from University of Catania in Italy.

Verification Futures Conference Presentation                                                               Video Presentation