Name:Andy Walton
Designation:Senior Member of Technical Staff, Verification
Challenges:
  • Working with the FPGA USP – flexibility
  • When the system-level verification environment is UVM…but the block-level isn’t
  • “But we can just run it on the hardware”…and sometimes they’re right!
  • Verification of designs which use partial reconfiguration.

Plus, most of the challenges facing ASIC/SoC verification teams!

Biography :   Andy specialises in verification in Altera’s Networking System Solutions Engineering group.  Andy received a BSc(Hons) in Computer Science from Manchester University in 1982.  He then spent 20 years developing networking products, 15 years of which were at DEC.  During this period he held a variety of roles, varying from ASIC and software development to architecture and project management. More recently, Andy worked for 8 years at Mentor Graphics, first managing IP development and then for 6 years as a Senior Verification Consultant, before joining Altera in 2011.

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