|Designation:||Functional Verification Specialist|
|Title:||Next Generation SoC Interconnect Architectures and their Impact on Verification|
Abstract : The strategy behind increasing SoC performance has transitioned from faster clock speeds to multi-core designs. But you can aggregate several multi-core clusters while unknowingly limiting system-level performance by ignoring cache coherent interconnect functionality and performance. This session describes two multi-core system level interconnect specifications, one optimized for mobile market designs, the other optimized for compute-intensive applications, and how they both address performance and low power system level requirements. The presenters will also discuss the verification challenges they present, and techniques available for ensuring optimal interconnect functionality, performance, and cache coherency.
Biography : Mark Olen is currently a Functional Verification Specialist at Mentor Graphics Corp. He has spent thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent test bench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first test bench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech’s thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Test bench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.
Video Presentation is unavailable at the request of Mentor Graphics