Name:Tim Joyce
Designation:Verification Manager

  • how do you work out how much resource you need?
  • where do you get that resource from?

Functional Coverage

  • what haven’t you covered when you’ve finished your SoC functional tests?

SoC Simulation Complexity

  • increasing IP count of SoCs means slower simulations
  • increasing number of SoC external interfaces means increasing testbench complexity

Biography :  Tim has over 20 years’ experience of functional verification. He graduated from Imperial College, London with a degree in Electrical Engineering in 1984. He then joined Inmos, working as a product engineer initially for the Transputer, and then Graphics Products families, before moving to the design and verification of those products. STMicroelectronics, who acquired Inmos, had a joint partnership with NVIDIA, and then Imagination Technologies, to produce PC Graphics 3D accelerator SoC products, and Tim was responsible for ST’s side of the functional verification of those projects. After ST left the PC Graphics market, Tim joined the Set Top Box Product Division, where he has spent the last 10 years as Verification Manager for their large-scale consumer SoC designs. The closure of the ST Bristol site early next year will require a change of role!

Verification Futures Conference Presentation                                                                                Video Presentation