|Name:||J. U. Nambi|
|Title:||Generation and Visualization of Multi-Threaded Multi-Core Test Cases|
Abstract: Today’s system-on-chip (SoC) projects are facing a verification challenge. Engineers are finding it hard to develop an effective full-chip testbench using the existing methodologies. The primary alternative, hand-writing C tests to run on the SoC’s embedded processors, is time-consuming and limited because humans can’t visualize multi-processor tests running in parallel. Hardware-software co-verification using emulation or an FPGA prototype is also limited since production software is well-behaved and available very late in the project. This talk discusses an alternative: Automatic generation of multi-threaded, multi-core, self-verifying C test cases. These are very effective at finding bugs and are more reusable that any of the alternatives. The talk also covers unique visualization capabilities to follow these automatic test cases and debug the design bugs they uncover.