|Title:||The Technology of Debug: Turning Art into a Science|
Abstract : When users are asked to list their verification challenges, debug consistently appears at or near the top of the list. Even as verification has moved from directed tests towards a methodical “science”, debug has remained an “art”. Furthermore, many debug “artists” have to work in multiple media, making it harder for their talents to be productively re-used. When we add on the additional complexity of debugging designs in the presence of the embedded software, then debug can easily become non-deterministic and open-ended.
To address these debug challenges, Synopsys is taking a lead in providing productive debug environments, applicable in verification flows based on all simulators, all languages and all methodologies. Synopsys’ debug solution, built on top of the Verdi3 advanced debug platform, solves the most complicated SoC debug problems, all the way from RTL to gate-level design.
This presentation will overview some of the technologies underpinning Verdi3’s success, including Siloti, for debug visibility optimization, Verdi3 Power-Aware Debug for low power debug and ProtoLink for prototype debug.
We will also introduce Verdi3 HW-SW Debug, for instruction-accurate embedded processor debug, raising productivity in this critical area.
Biography : Bindesh Patel is a Technical Manager at Synopsys, having joined as part of the Springsoft Acquisition in 2012 and having previously worked in Design and Applications Engineering at LSI Logic, Zycad, and Atrenta.
Bindesh is responsible for defining future verification and debug products within Synopsys’s Verification Group. He is also actively involved in Accellera initiatives such as the ViP committee working on the UVM standard verification library and methodology. No stranger to presenting at technical conferences, having served on the DVCon Technical Program Committee for several years, Bindesh has written many articles and conference papers on verification and debug topics.
He has a degree in Computer Engineering from the University of California, Santa Cruz.
Slides and Presentation will follow shortly