|Designation:||Senior Member of Technical Staff|
|Title:||To be confirmed|
Abstract : To be confirmed
Biography : Jon holds a Master’s degree in electronic engineering from Southampton University and has worked at a variety of different technology companies in the UK, in a variety of roles, including system design at ICL, ASIC design at Sony semiconductors and Lucent microelectronics (Agere) and IP design for FPGA at Altera. He has consulted on physical design and timing closure for Imagination technologies and Infineon whilst at Sondrel. He has over 20 years experience of coding IP and test infrastructures in Verilog and System Verilog and leads Altera UK’s expert verification group which facilitates communication on verification strategies between Altera’s different divisions and helps to direct verification strategy within Altera. He has architected the verification library for Altera’s video IP cores which is shipped with the Quartus design suite and is available for use by customers. Jon is a chartered engineer and an IET member and technical reviewer. He has a passion for science and engineering, has presented at the NMI, given talks on electronics at the local primary school and has written a children’s book, Noosum Foosum, which features an engineer as the lead character.
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