|Designation:||CEO and Founder|
Abstract : The increase of SoC complexity with more cores, IPs and other subsystems has led SoC architects to demand more from the main interconnect or NoC, which becomes a key component of the system. Power management, multiple clock domains, protocol conversions, security management, virtual address space, cache coherency are now key features that the main interconnect needs to manage and which demand proper verification.
In addition, IP reuse and Network-on-Chip (NoC) generation solutions have enabled the conception of new SoC architectures within a few months if not only weeks. While a simple point to point scoreboard methodology is taught in all good verification methodology books or tutorials, building a generic verification solution for SoC interconnect that can quickly adapt to any bus protocols, SoC architectures and deal with SoC advanced features is much more than dealing with point to point transaction matching.
At Test and Verification Solutions (TVS) we have developed a UVM NoC Scoreboard VIP to provide a generic approach for interconnect, fabrics and NoC verification and accelerate this verification.
Biography: Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering and an MBA from the Open University, and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide.
Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.