Bangalore, India
Tuesday, 13 May 2014

08.30Arrival: Networking
09.15Introduction: Mike Bartley, Test and Verification Solutions Ltd
09.20Panel Session: Challenge Papers – Our Top Verification Challenges

09.50Synopsys, Amit Sharma, (Senior CAE Manager, Verification BU)
10.10Cypress Semiconductors, Vijayabhaskar Sankaranarayanan (Senior Engineering Manager)
10.30Refreshments and Networking
11.15User Presentations

12.35Jasper Design Automation
12.55Lunch and Networking
14.10Mentor Graphics, Ajay Goyal (Verification Technology Manager)
14.30Texas Instruments, Vinod Paparaju (Senior Design Engineer)
14.50Test and Verification Solutions Ltd, Gaurav Maheshwari (Engineering Manager – Software)
15.10Refreshments and Networking
15.40Doulos, John Aynsley (CTO)
16.00Panel Session: The EDA response
16.45Concluding Remarks, Mike Bartley
17.00Meet the sponsors in the Exhibition Area
18.00End of Conference

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