|Designation:||Verification Technology Manager|
|Title:||Next Generation SoC Interconnect Architectures and their Impact on Verification|
Abstract: The strategy behind increasing SoC performance has transitioned from faster clock speeds to multi-core designs. But you can aggregate several multi-core clusters while unknowingly limiting system-level performance by ignoring cache coherent interconnect functionality and performance. This session describes two multi-core system level interconnect specifications, one optimized for mobile market designs, the other optimized for compute-intensive applications, and how they both address performance and low power system level requirements. The presenters will also discuss the verification challenges they present, and techniques available for ensuring optimal interconnect functionality, performance, and cache coherency.
Biography: Ajay Goyal has 14+ years of experience in EDA and is working as Verification Technology Manager in Mentor Graphics. He has worked in multiple areas like Advance Verification, Emulation and System Level domain like High Level Synthesis, TLM based Design and Verification, Virtual System Platform. His areas of expertise are Emulation, Advance Verification and High Level Synthesis. He completed his BE from Nagpur University in 1999 and MBA from Symbiosis Institute of Management studies, Pune.