Name:Amit Sharma
Designation:Senior Manager, Corporate Applications Engineering
Title:The next order of verification productivity and performance through new technology, massive integration, and methodology

Abstract:  SoCs are transforming the electronics industry by integrating a staggering amount of functionality into high-performance, low-power, single-chip implementations with embedded software. Inevitably, as SoCs become larger and more complex driven by the convergence of functionalities, they strain the performance and productivity of verification methodologies and tools.

Verification tools have served fairly well, but are increasingly limited by the complexity of simultaneously validating different abstraction levels.  The combination of abstraction levels and verification flows introduces new classes of failure modes impossible to verify by any single method. This has led to a new paradigm of verification by massively integrated techniques. Recently introduced in Verification Compiler, this concept integrates many novel technologies that lay the foundation for future technology breakthroughs.  This presentation sheds some light on Verification Compiler embodies a fundamental rethink of SoC verification.

Biography: Amit Sharma is a Senior Manager in the Verification Group in Synopsys India. Amit joined Synopsys twelve years ago after completing his Graduation in Electronics and Communication  Engineering from NIT, Surathkal. Initially, he worked extensively on architecting and implementing Verification environments in HVLs and in various facets of functional verification of networking chips and protocol, microprocessors and system level platforms. Over time, he honed his engineering skills and gained a business background by completing his MBA from the Indian Institute of Management, Bangalore. Currently, he manages several key customers with whom he shares his experience in testbenches, verification methodologies and simulation technologies. He has been a speaker in multiple forums. This  includes multiple presentations in DVCON,DAC, tutorials in various editions of SNUG in different geographies, presentations on different aspects of verification productivity  in the DVM and ESLD workshops held by the VLSI society of India.