|Name:||Varun Aggarwal (Staff Engineer)Amit Chhabra (Staff Engineer)|
|Title:||Low Power Verification of ARM CPU Sub-System using IEEE 1801|
Abstract: Modern day CPU subsystems need to support very high speed and ultra-low power at the same time, to have adequate user experienceand longer battery life respectively. This is achieved by deploying multiple low power techniques like dynamic voltage and frequency scaling (DVFS), body voltage modulation (body biasing), shutdown, retention, etc. which in turn manifest themselves as a new dimension in design verification in context of power intent, powersequences,states, et al. This paper describes low power simulation based techniques to verify power intent (IEEE1801-UPF2.0) and power sequences in tandem with power management IPs like power switches, power controllers, body bias IPs, etc. in ARM based CPU subsystem design.
Amit Chhabra received his B.Tech. in Electrical Engineering from Indian Institute of Technology Delhi in 2002. He joined memory solutions group in STMicroelectronics, India in the same year. He has worked on memory design, and is currently involved in design of SRAM process sensors and adaptive memories. In addition to memories, he is involved as a low power expert for memory power reduction at architecture level.
Varun Aggarwal isa B. Tech. graduate from Indian Institute of Technology Guwahati in ECE, having 8+ years of experience in front-end design and verification. He has worked extensively on IP-level functional verification. Presentlyhe is working with CPU Subsystem teamat ST Microelectronics for low power verification using simulation and formal techniques.