Name:Vishwanath Herur
Designation:Principal Engineer
Title:Prototyping Challenges

Abstract:  Larger designs like SOC’s pose significant requirements on systems and tool as With very high integration on FPGA’s  ,  A solution seems to be emerging but with its own challenges.

Biography:  Vishwanath Herur has a total of 21 years of work experience working in the areas of verification and validation. He received a B.E in Electronics and Communication from SJCE Mysore in the year 1993 and MS in Electronics and Controls from BITS in the Year 1997. He has been working in the areas of Pre silicon verification, System level validation using simulation, Emulation and FPGA prototypes. Presently he is working at ARM for the past 3 years and  developing system level validation flows for FPGA prototypes