Conference:Verification Futures 2015 (click here to see full programme)
Speaker:Graham Reith, Industry Manager: Communications, Electronics & Semiconductors
Presentation Title:Reducing the Cost of FPGA/ASIC Verification with MATLAB and Simulink
Abstract:Recent developments in MATLAB® and Simulink® reduce the cost of developing FPGA and ASIC applications, through providing strong integration with conventional EDA workflows. This includes not only the efficient generation of RTL for implementation of algorithms, but also the generation of effective test benches to aid verification for both digital and mixed-signal systems.

  • Generate VHDL® or Verilog® code from MATLAB, Simulink, and Stateflow® for FPGA or ASIC implementation
  • Develop system-level testbenches in MATLAB and Simulink, and reuse for RTL verification through cosimulation with EDA tools and through FPGA-in-the-loop methods
  • Export models from MATLAB and Simulink to other verification environments, including SystemVerilog and SystemC/TLM
BiographyGraham Reith has been with MathWorks since 2002, and has over 15 years of experience applying MathWorks tools to the development and implementation of signal processing and communications systems. He currently focuses on the adoption of MathWorks technology in EDA design flows within the Communications, Electronics and Semiconductor industries across Europe and China.At MathWorks Graham previously worked as an Application Engineering Manager, with a team focussing on Signal Processing and Communications applications. Prior to joining MathWorks he worked in applied research for the UK Government, developing high performance embedded signal processing applications on DSP and FPGA. This included work on demodulation, equalisation and beamforming algorithms, as well as some RF circuit design. Graham graduated with a Masters degree in Electronic Engineering from the University of York, United Kingdom.