With ever increasing pressures on IC development teams to reduce timescales and costs while the complexity of the products they are developing is increasing, it is becoming ever more important to not only improve productivity, but also to do so in predictable manner if deadlines and costs are to be met. This presentation will highlight the key challenges in achieving predictable verification productivity in DisplayLink’s IC development process.
Getting even greater re-use of FPGA and simulation platforms within multiple discipline teams.
Spending less time fixing RTL and testbench bugs.
Spending less time fixing bugs in third party tools, IP and VIP.
Wez graduated from the University of Warwick in 1990 with a BSc. degree in Computer Systems Engineering, with an aspiration to work in VLSI. After a short spell with British Aerospace, he joined GEC Plessey Semiconductor (later Mitel Semiconductor then Zarlink Semiconductor) where he started his journey in IC development. Starting with developing standard cell libraries and EDA flows he moved on to lead teams in the design and verification of ASICs for internal and external customers. Wez joined DisplayLink in 2006 to specialise in verification and has since then led DisplayLink’s verification team in developing DisplayLink’s innovative network display products, including the latest DL-5500 USB to 4K/Ultra-HD IC.