Breker Verification Systems




Name: Frederic Krampac
Designation: Senior Applications Engineer
Title:Break Your SoC with Automatically Generated C Test Cases


SoC teams are finding it impossible to verify a full-chip design from a testbench alone. Inner portions of a large, complex chip are hard to control from the inputs, so deeply buried bugs aren’t discovered until prototyping or final silicon. Since the power of the SoC lies in its embedded processors, many teams write tests to run on the processors in simulation to supplement their testbench verification. However, hand-writing tests takes a great deal of time and effort, rarely resulting in real-world application scenarios or any significant degree of concurrency.

This talk presents an alternative: automatically generated, self-verifying C test cases that run on your SoC’s embedded processors. These test cases try to “break” the SoC with multi-threaded scenarios that represent actual use cases. A high degree of concurrency saturates buses and I/O channels while deviously planned memory allocation looks for overlaps and misalignment. This approach stress-tests every aspect of your SoC design, finds deep bugs in simulation before they escape to silicon, and enables performance measurement under realistic conditions.


Frederic Krampac is a Senior Applications Engineer at Breker Verification Systems. He has worked on projects involving chip-level integration, IP verification, VIP development, system-level modeling, and software design. Prior to Breker, he was Verification Consultant in the Services group at Synopsys, working for customers worldwide. He has also held EDA engineer positions at Texas Instruments and STMicroelectronics. He holds a degree in Electrical Engineering from Polytech’Montpellier and Politecnico di Torino.

Verification Futures Conference Presentation