Name:Michael Rohleder
Designation:Design Architect, Senior Member of Technical Staff
  • Verification of synthesis constraints as well as STA / timing constraints and their correct application during development.
  • Determine the coverage of a testbench consisting of directed, random stimulus, but also formal verification tests in light of a staged verification process (module level, platform, SoC)
  • Disconnected viewpoints of a design that should be verified in conjunction (multi-mode architectures, power connectivity and domains, analog aspects that need to be verified in conjunction with digital logic, behavioural models)


Michael is design architect within Freescale’s New Product Development Center based in Munich. During his 20+ years with Motorola/Freescale he participated in the development of several SoC’s, system level simulation and design, led process improvement activities, and was one of the architects of Freescale’s common design system as well as the common testbench and device architecture used by the Joint Development Program of Freescale/ST Microelectronics. He is also participating in several standardisation efforts (SystemVerilog IEEE-1800, UVM) and was one of the drivers behind the ISO26262 certification of the MPC5643L device. Now he is concentrating on device architecture, functional safety, verification automation and many other methodology aspects. Michael holds a Dipl.-Inform. from the Technical University of Munich.

Verification Futures Conference Presentation            Video Presentation