Jasper Design Automation





Name:Stefan Staber
Designation:Senior Application Engineer at Jasper Design Automation
Title:Leveraging Formal Verification Throughout the Entire Design Cycle


Formal is typically seen as a point tool with limited scope and is usually only applied to a small subset of design and verification challenges. However, with the right supporting technologies and features, the benefits of formal verification can be leveraged throughout all stages including:

  • Stand-alone verification of architectural protocols
  • Designer sandbox testing for RTL development
  • End-to-end data packet integrity
  • SoC connectivity and integration verification
  • Root-cause isolation and full proofs during post-silicon debug

Traditional verification methods of the above areas are becoming more of a challenge as design complexity increases, but formal verification can be a valuable addition. For example, applying formal techniques early in the design cycle to exhaustively verifying block-level design functionality can produce higher quality RTL delivered to unit and system level verification. Attendees will learn about Jasper’s unique formal technologies and flows that enable designers and verification engineers to augment existing flows. Also included will be discussions about how effort applied to one application can be leveraged in others. We’ll explore new areas that Jasper Formal technologies are addressing including coverage closure, system-level deadlock, low power, and sequential equivalency checking.  When applied intelligently, Jasper formal technologies can enhance traditional design and verification flows to help reduce the risks associated with increasing SoC complexity.

Verification Futures Conference Presentation             Video Presentation

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