Verification Futures : United Kingdom 2012The 2012 Verification Futures conference series was a resounding success with 472 participants from 200 companies across 27 countries! We have presentations and recordings available to review, just use the links below.
Agenda
8.30 | Arrival: Refreshments and Networking |
9.15 | Introduction: Mike Bartley, T&VS |
9.20 | Mentor Graphics – Harry Foster, Chief Scientist |
10.00 | Panel Session: Challenge Papers – Our Top Verification Challenges |
10.40 | Synopsys – Janick Bergeron, Scientist and Fellow |
11.00 | Refreshments and Networking |
11.30 | User Presentations- Dialog Semiconductor – Steve Holloway, Senior Verification Engineer
- Imagination Technologies – Theo Drane, Principle Design Engineer
- Test and Verification Solutions – Francois Cerisier, Manager T&VS France
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12.30 | EVE – Luc Burgun, CEO and President, Emulation & Verification Engineering S.A |
13.00 | Lunch and Networking |
14.00 | Jasper Design Automation – Stefan Staber, Staff Field Application Engineer |
14.20 | Doulos – John Aynsley, CTO |
14.40 | Cadence – Nick Heaton, Senior System and SoC Solutions Architect |
15.10 | SpringSoft Inc – Jean-Marc Forey, Technical Marketing Manager |
15.40 | Refreshments and Networking |
16.10 | Aldec Inc – Jacek Majkowski, Senior Hardware Engineer |
16.40 | Panel Session: The EDA response |
17.25 | Concluding Remarks from Platinum Sponsors (Mentor Graphics, SpringSoft Inc, Cadence, EVE, Aldec) |
17.40 | Meet the sponsors in the Exhibition Area |
18.15 | End of Conference |
Event Sponsors
