Verification Futures Europe 2016 - T&VS

Verification Futures Europe 2016

Verification Futures is a unique one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe.

Overview

When:	Thursday, 4 February 2016
Where:	Reading, UK – Holiday Inn, Wharfedale Road, Winnersh Triangle, Reading, RG41 5TS (M4 J10)

Agenda

08:30

Registration, Coffee and Networking

09:25

Welcome: Mike Bartley, Test and Verification Solutions Ltd.

09:30

Keynote Presentation:
The Next Generation of Verification Innovation
Fabian Delguste, Synopsys

10:00

User Top Verification Challenges

Top Verification Challenges – Steve Holloway, Dialog
Top Verification Challenges – Andy Bond of Cirrus Logic
Top Verification Challenges – Jon Buckingham, Hewlett Packard Enterprise

EDA Presentations

10:30

What You See Is What You Get Verification With Vtool – Asi Lifshitz, Vtool

10:50

Fault Analysis – What Is Your Real FIT Size – Avidan Efody, Mentor Graphics

11:10

NMI – Your Champion for the UK Electronics Systems Industry – Pete Davy, NMI

11:15

Refreshments, Networking & Meet the Sponsors

11:45

Multi-track Sessions

Track #1: ASIC
Chaired by: Mike Bartley, T&VS

Agile Design Using Properties and Formal Tools – Jon Buckingham, Hewlett Packard Enterprise
FPGA Accelerated IP Validation – Andrew Gardner, ARM
Making the most of your MATLAB Models to Improve Verification – Graham Reith, Mathworks

Track #2: FPGA
Chaired by: Pete Davy, NMI

FPGA Verification: The NMI Survey Says . . . – Doug Amos, Mentor Graphics on behalf of NMI
Exploitation for Fun and Profit – Chris Higgs, Potential Ventures
Applying Agile Techniques to the Development of Safety Critical Software – Gary Sheppard, GE

12:45

Lunch and Networking

13:45

Managing a Secure Requirements Engineering Flow Within a Complex Product Family Environment in Order to Attain ISO26262 Compliance – Serrie-justine Chapman, T&VS

14:05

Is Your Code as Cool as Expected? – Kyriakos Georgiou, University of Bristol

14:25

Standards and Architecture Considerations for Secure Hardware Design and Verification – Richard Marshall, Xitex

14:45

Refreshments, Networking & Meet the Sponsors

The EDA Responses

15:15

Rethinking Coverage in a Multi-Verification Tool Environment – Jörg Große, OneSpin Solutions

15:35

2016 Challenges and Beyond – Nick Heaton, Cadence

15:55

Accelerate Your Next ASIC: Introducing the FPGA Co-emulator
Alex Grove, First EDA

16:15

Panel Discussion – How Can We Solve The Challenges? Panel of experts drawn from the speakers and user community including representatives from: Synopsys, Vtool, Mentor, Cadence, OneSpin and Aldec.

16:45

Meet the Sponsors in the Exhibition Area

17:00

Event Closes

Agenda and timings subject to change.