Conference:Verification Futures 2016 (click here to see full programme)
Speaker:Avidan Efody (Verification Architect)
Organisation:Mentor Graphics
Presentation Title:Fault analysis – What is Your Real FIT Size?
Abstract:Accurately measuring a component’s Failures In Time (FIT) is key to keeping designs as simple as they should be, and avoiding over-design and schedule risks. To obtain ISO 26262 certification, users are required to calculate FIT rates and a set of derived “architectural metrics” that allow objective assessment of their safety concept. In this session we will discuss fault de-rating techniques available at various abstraction levels, and explain how they should all be combined to get a realistic estimate of FIT numbers and ISO 26262 architectural metrics.

  • What is FIT? What is base FIT?
  • How is FIT de-rated at various abstraction levels?
  • Techniques for FIT de-rating at RTL/Gate
Speaker Bio:Avidan Efody is a verification architect for Mentor Graphics, and an expert in listening to customers, distilling their problems, and helping them get to the optimal solution, preferably using Mentor tools. Prior to moving to EDA Avidan has been architecting and coding testbenches in a variety of languages/methodologies for a variety of companies including PMC-Sierra, Infineon, TI, Nokia-Siemens and others.

Recent problems he has been called to solve are fault analysis according to ISO 26262 specification, removal of adoption barriers for advanced verification methodologies within ISO 26262 and DO 254 flows, AMBA interconnect verification, Matlab-RTL integration and a few more. He’s proficient in SystemVerilog, OVM, UVM and a multitude of scripting languages such as Perl, TCL, PHP and JavaScript