Verification Futures 2020

Conference:Verification Futures 2020 (click here to see full programme)
Speaker:Bryan Dickman, Independent Consultant, Valytic and Joe Convey, CEO (Acuerdo)
Presentation Title:On the Cost of Bugs
Abstract:Critical bugs occur in complex hardware IP products such as processors and GPUs, either during development or post release; what is the true cost? We want to explain how to get a better understanding of this cost; how can it be used to guide development and methodology investment decisions to avoid, or mitigate this risk?

We will consider all aspects of the cost impact including less well understood areas such as opportunity costs and reputational costs, and consider the cost impact across the whole ecosystem from IP developer, to licensee and product developer, software ecosystems and end users.

We will explore ways to model cost impacts and how those models can be used to drive product development decision making processes.

This presentation follows on from “On the Origin of Bugs”  presented at DVClub in November 2019.

3 Key Points:

  • Design Verification is a time and resource-bounded quest to find all hardware bugs prior to product release – some will inevitably be missed. Some of these bug escapes may be critical with far reaching impacts.
  • The cost impact of bugs needs to be understood from many angles. It goes much further than the simple rework cost of fixing and re-verification. Understanding and modelling these impact costs helps product development teams to reason about product development engineering costs from an ROI point of view.
  • Famously the Intel FDIV bug cost Intel an estimated $475M in 1995. This was just the direct impact cost to Intel. How much would a similar disastrous bug cost a developer and then the entire ecosystem today. Recent security bugs such as Spectre and Meltdown are likely to have far reaching cost implications across the industry.
Speaker Bio:1. Bryan Dickman: Over 22 years of leading engineering teams and engineering communities in the field of design verification for Arm Processors. In recent years, more focused on leading the effort to exploit Engineering’s vast data resources to drive insights and improvements to critical workflows. Currently working as an independent consultant and founder of Valytic Consulting Limited.

2. Joe Convey: 14+ years in semiconductor and EDA. Close relationships with engineering management to understand needs and provide best-in-class engineering platform. Promoted commercial awareness in engineering teams, showing the value of Partnership with EDA vendors as a methodology to get optimised results from their tools and services. In-depth experience of negotiation with major EDA vendors to ensure delivery of a resilient platform within acceptable commercial limits.