Wafer-level packaging(WLP) enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.

This article from Semiengineering describes how uniting package design environments with SoC physical verification tools ensures the necessary co-design and verification platforms are in place.

Read More

Find how T&VS SoC Verification Services ensures greater efficiency, improve debug, faster time-to-market, and gives design teams the ability to de-risk the challenges of complex chip designs.