Design verification is running on emulators and prototype platforms on more of the software stack, in order to provide confidence and coverage across a range of use models. These factors together mean significant components of the design and overall SoC verification are increasingly centered on software rather than RTL.

This article from SemiWiki describes how Mentor has built the solution to address both design and verification together at high-level design by recognizing this shift.

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Find out how T&VS discover multiple bugs in the RTL and allows the customer to validate the SoC design through execution of software.