Join Venkatesh Vasudevan of TVS at DVClub Europe on Monday, 8 September 2014, where he will present on using Approximately Timed (AT) Modelling for Performance Modelling of Designs. Venkatesh will explain the concepts and how they have been applied to performance modelling of System-on-Chip (SoC) blocks including LPDDR4 Memory Controller, AXI4 bus etc. Custom phases have been introduced where applicable and the TLM 2.0 Generic Payload is used as much as possible.
You can reserve your place at one of our venues in Bristol, Grenoble and Sophia. If you are unable to attend the DVClub in person, why not join by Remote Access.