The Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions in SystemVerilog to find and fix bugs. The workshop explains how formal verification differs from simulation, the advantages and drawbacks, and how to effectively incorporate formal into a design flow. The workshop uses a small worked example and the delegates prove some ready-made SystemVerilog Assertions using a tool during the workshop. Delegates are also asked to extend the assertions and to also use cover properties to visualise the design and to measure coverage. The workshop ends with a thorough analysis of the strengths and weaknesses of formal verification. It shows how others have exploited formal and successfully incorporated it into their design flow.
Delegates should leave with enough knowledge to be able to understand how they could potentially adopt formal verification and perform an effective evaluation of tools.