Constrained random verification is a standard industry approach to test digital intellectual properties which has been widely adopted in today’s hardware verification flows. An inefficient constraint solver impacts the overall verification effort by long runtimes for stimulus generation, whereas a highly skewed distribution can dramatically increase the number of simulation steps required to execute a target transition of the design.

This article from Design reuse outlines why the effective constraint solver is necessary to increase the overall verification efficiency and generate regressions.

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Find how T&VS helps Verification Engineers efficiently improve the verification productivity by utilizing the constraint solver.