Reducing the Cost of FPGA/ASIC Verification with MATLAB and Simulink

Recent developments in MATLAB® and Simulink® reduce the cost of developing FPGA and ASIC applications, through providing strong integration with conventional EDA workflows. This includes not only the efficient generation of RTL for implementation of algorithms, but also the generation of effective test benches to aid verification for both digital and mixed-signal systems. Learn more about this at Verification Futures.

Verification Futures, held on February 5th in Reading and online, is a unique free one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions.

Register here.

2015-02-02T09:35:03+00:002nd February, 2015|Active Event, Blog, Events|