Verification IP – Trends and Technology for FPGA and ASIC Design Verification

Adam Rose of Mentor Graphics will introduce and discuss new EZ-VIP  for PCI Express that provides re-usable building blocks for common protocols and architectures for reduced testbench assembly time for FPGA design verification at Verification Futures

Verification Futures, held on February 5th in Reading and online, is a unique free one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions.

Register here.

2015-02-02T09:45:26+00:002nd February, 2015|Active Event, Blog, Events|