In high-reliability and safety-critical applications,RT and gate-level fault-injection simulations are often performed in order to ensure a certain level of fault detection coverage which is necessary to ensure compliance with standards such as ISO26262.

This article from Mentor Graphics describes the architecture for a complete fault injection platform and outlines how this architecture can be easily integrated into a general purpose design verification environment (DVE) that is implemented using UVM. Read More

Find out how T&VS Verification Services helps to design a challenging fault-injection platform that can be re-used effectively across designs.